fig. 01 — the SKU

One model, and exactly what supported means.

tiyuvta inference serves the Qwen 27B class and nothing else. One model, served obsessively, beats a thousand-model menu on every quality axis a small fleet can control. This page is the whole catalog: the SKU, the gate battery it passed to be listed, and the measured board.

qwen3.6-27b Qwen 27B class · 8-bit, bit-audited

model id

qwen3.6-27b is the string you pass as model. It is pinned — never silently remapped to different weights, a different precision arm, or a different template.

precision arms

Q8_0 GGUF is the shipping 8-bit serving arm. FP8-E4M3 safetensors checkpoints (block-128 scale grids, including the official Qwen/Qwen3.6-27B-FP8) load, gate green, and serve — dequantized to the Q8_0 arm byte-identically, verified on the official artifact with prefill logits bit-identical at 993280/993280 bytes. GPU-side FP8 dequant cuts the 29 GB load wall 2.89x and is available opt-in. A native per-block FP8 MMQ tile is implemented and bit-exact but does not yet clear our 1.1x deployment bar, so it stays off by default. A lossy per-tensor scale fold buys 18.4% prefill and is not shipped — it changes what the model says. FP8 load and bit-identity measured on a rented 2x RTX 5090 box; the format decision is a published document, not a footnote.

context

40,960 tokens.

speculative decode

On by default on the NVFP4+MTP leg. It changes speed, not output: K=1..8 self-consistency is a standing gate, run on the MTP-capable artifact.

supports

streaming
tools
json_schema
prefix cache
cache_salt
seed
session affinity
per-tenant keys

pricing

Per-token interactive or a reserved dedicated replica; cached input discounted and itemized on every response. See pricing →

Qwen3.8-27B: a day-one bring-up runbook is written and ready ahead of the expected release. Step-3.7-Flash: bring-up is in flight as the planned flagship. Either model appears on this page only after its gate battery goes green — the battery is the listing gate, and nothing is guaranteed before it passes.

fig. 02 — what supported means here

The gate battery is the listing gate.

A model does not appear on this page because a checkpoint loads. It appears because it passed this battery, and it stays only while the battery stays green. Each row links the document that defines the gate.

gate	what it checks	state	receipt
kernel-check	every CUDA kernel bit-audited against a CPU reference — run naked and again model-backed on the real 27B weights; one mismatch voids every number after it	ALL GREEN	research/pro6000-prod-20260804
run-gen argmax	greedy generation argmax-compared against the reference path on real prompts, both precision arms	MATCH	research/pro6000-prod-20260804
run-spec self-consistency	K=1..8 self-consistency is a standing gate, run on the MTP-capable artifact; the production board ran K=1..3 as its listing gate	PASS	docs/TESTING.md
serve isolation	greedy output byte-compared alone vs inside a full batch (c=1 vs c=16, same server, every stream replayed) — 16/16 on four models at defaults	PASS	docs/SERVING.md
deployment bar	speculative decode must clear ≥1.1x end-to-end over our own plain decode with an own-generated trimmed drafter before the word supported is used — measured 2.17x on this SKU	PASS	research/pro6000-prod-20260804

fig. 03 — the board

The measured board.

measured 2026-08-04 · RTX PRO 6000 Blackwell 96GB (rented pod) · N=5 / N=3 medians — not owned hardware; the owned build-out targets the same silicon

surface	measured	conditions
decode, spec (NVFP4+MTP leg), serve surface	170.5 tok/s	single stream, c=1, through /v1/chat/completions — N=5 median
decode, spec (NVFP4+MTP leg), bare CLI	186.7 tok/s	single stream, no serve surface — N=5 median
decode, plain, NVFP4 arm	86.8 tok/s	tg128 at a 512-token prompt — N=5 median
decode, plain, Q8_0 arm	52.6 tok/s	tg128 at a 512-token prompt — N=5 median
aggregate throughput, c=8 — the knee	420.6 tok/s	NVFP4 arm, batched serve, N=3 median; beyond c=8 latency doubles per step for flat throughput, so c=16/32 is queueing, not capacity
aggregate throughput, c=8, Q8_0 arm	308.7 tok/s	batched serve — N=3 median
TTFT, cold	0.182 s	a fresh cache_salt per request forces a real cache miss — N=5
TTFT, warm	0.003 s	prefix-cache hit, same protocol — N=5
prefill pp512, NVFP4 arm	4118 tok/s	N=5, arms interleaved within every rep
prefill pp512, Q8_0 arm	4591 tok/s	N=5, interleaved — a different artifact than the NVFP4 row, not a configuration of it

This is a dated static board rendered from receipt JSON at build time — not live telemetry, and not pretending to be. It changes when the receipts change. Cold and warm TTFT are always separate cells: an unsalted repeat request hits the prefix cache, so a TTFT number without a fresh cache_salt is a warm number wearing a cold label. Raw logs: research/pro6000-prod-20260804.

fig. 04 — versioning

Model ids are pinned

qwen3.6-27b means the same weights, the same precision arm, and the same template until a dated announcement says otherwise.

Builds are fingerprinted

Every response carries the engine build in system_fingerprint, so an eval run can be pinned to the exact build that produced it.

Changes carry dates

Anything that can move an output — weights, kernels, template, defaults — is announced with a date on the lab's evidence ledger before it ships.

A short catalog is deliberate. If your workload needs a different model, request it — bring-ups in flight are named above with their receipts, and nothing is promised ahead of a green gate battery.